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seminars:unlocking_the_full_potential_of_persistent_memory_technique_with_software_hardware_coordinated_design [2018/09/27 09:18] (current)
zzhao1 created
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 +====== Unlocking the Full Potential of Persistent Memory Technique with Software/​Hardware Coordinated Design ======
  
 +Friday October 5, 2018\\
 +Location: CIC 4th floor Panther Hollow Conference Room\\
 +Time: 12:​00PM-1:​00PM\\
 +
 +
 +
 +=====Abstract=====
 +
 +Persistent memory is a new tier in the memory/​storage stack. It offers the fast access of memory and data recoverability of storage in a single device. Seeing the great value, many computer hardware and software suppliers have recently begun to adopt persistent memory in their next-generation designs. Though promising, persistent memory fundamentally changes current memory and storage system design assumptions. Unlocking its full potential is not easy. In this talk, I will present my research on software/​hardware coordinated mechanisms that efficiently exploit persistent memory techniques to maintain the reliability of memory hierarchy. While most previous persistent memory designs manipulate data persistence by software, we identify that abundant opportunities exist in maintaining data persistence at much higher performance by leveraging existing memory hierarchy hardware ​ mechanisms. I will present our recent study on hardware-driven undo+redo logging, which  maintains ​ data  persistence by leveraging the write-back, write-allocate policies used  in commodity ​ caches. Our evaluation ​  ​across ​  ​persistent memory ​ micro-benchmarks and real workloads demonstrates that our design significantly improves system throughput and reduces both dynamic energy and memory traffic. Furthermore,​ we identify that the persistent memory technique can be leveraged to enable high-performance and highly reliable memory hierarchy ​ design, when scaling up memory capacity. I will present our study on a coordinated memory hierarchy reliability scheme, which coordinates (i) reliability mechanisms between CPU's last-level cache and nonvolatile main memory and (ii) nonvolatile memory wear-leveling with persistent data commits. As a result, our design achieves much better reliability than state-of-the-art resilience schemes.
 +
 +=====Bio===== ​
 +Jishen Zhao is an Assistant Professor in the Computer Science and Engineering Department at University of California, San Diego. Her research spans and stretches the boundary between computer architecture and system software, with a particular emphasis on memory and storage systems, domain-specific acceleration,​ and system reliability. Her research is driven by both emerging device/​circuit technologies (e.g., 3D integration,​ nonvolatile memories) and modern applications (e.g., big-data analytics, machine learning, and smart home and transportation). Before joining UCSD, she was an Assistant Professor at UC Santa Cruz, and a research scientist at HP Labs before joining UCSC.