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seminars:seminar_9_20_16 [2017/09/20 22:02] (current)
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 +====== Automatically Finding & Fixing Cache Contention Bugs ======
 +Tuesday September 20th, 2016\\
 +Location: HH 1107 [NOTE: Location changed from Panther Hollow Conference room at CIC]\\
 +Time: 4:30PM\\
 +**[[https://​www.cis.upenn.edu/​~devietti/​ | Joe Devietti (University of Pennsylvania)]]**\\
 +Multicore architectures continue to pervade every part of
 +our computing infrastructure,​ from servers to phones and smart
 +watches. While these parallel architectures bring established
 +performance and energy efficiency gains compared to single-core
 +designs, parallel code written for these architectures can suffer from
 +subtle performance bugs that are difficult to understand and repair
 +with current tools.
 +We'll discuss two systems that leverage hardware-software co-design to
 +tackle cache contention bugs like false sharing, in the context of
 +both unmanaged languages like C/C++ and managed languages like Java.
 +These systems use hardware performance counters for efficient bug
 +detection, and novel runtime systems to repair bugs online without any
 +programmer intervention. Along the way, we'll discuss some subtle
 +memory consistency model issues brought to light by these
 +Joseph Devietti is an Assistant Professor in the Department of
 +Computer & Information Science at the University of Pennsylvania. His
 +research focuses on making multicore computers easier to program,
 +leveraging techniques across the computing stack, including computer
 +architecture,​ compilers, runtime systems and programming languages. He
 +was awarded an Intel Early Career Faculty Honor in 2013. He earned his
 +PhD in Computer Science & Engineering from the University of
 +Washington in 2012.
 +**[[seminars| Back to the seminar page]]**