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seminars:seminar_3_29_17 [2017/09/20 22:02] (current)
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 +====== Power- and Performance-constrained Thread Mapping and DVFS on Heterogeneous Multi-Core Systems ======
 +Wednesday March 29, 2017\\
 +Location: CIC Panther Hollow Room\\
 +Time: 4:30PM\\
 +**Dimitrios Stamoulis (CMU)**\\
 +Modern many-core systems must cope with a wide range of heterogeneity
 +due to either the numerous processing components that are heterogeneous 
 +by design, or due to the different performance requirements of multi-application,​
 +multi-threaded workloads. This raises an important question for chip multiprocessor 
 +designers: Can we guarantee per-application performance constraints under 
 +workload and core heterogeneity,​ while staying within the power budget?
 +In this talk, I will present our work on an approach for simultaneous thread mapping 
 +and Dynamic Voltage Frequency Scaling (DVFS) on heterogeneous multi-core systems
 +to maximize overall performance,​ while satisfying the power budget and per-application
 +performance requirements. We formulate this optimization problem as a constrained 0-1 
 +integer linear program (ILP) and we propose a heuristic-based algorithm for efficiently 
 +solving it. Compared with an optimal solver, our method produces results less than 1.5% 
 +away from optimum on average, with four orders of magnitude improvement in runtime.
 +We also show that our method always meets per-application performance requirements,​ 
 +while agnostic approaches could result in performance bound violations up to 48.1%.
 +Dimitrios Stamoulis is a second year PhD student advised by Professor Diana
 +Marculescu. His research is focused on performance optimization for heterogeneous 
 +and dark silicon multi-core systems under power and variability constraints.
 +**[[seminars| Back to the seminar page]]**