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seminars:seminar_3_18_15 [2017/09/20 22:02] (current)
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 +====== Coming to Terms with the End of DRAM Scaling ======
 +==== Yoongu Kim (CMU) ====
 +== Wednesday 3/18, 4:00-5:00pm ==
 +== CIC Panther Hollow ==
 +===== Abstract =====
 +For decades, main memory has enjoyed the continuous scaling of its physical
 +substrate: DRAM. But now, DRAM scaling has reached a threshold where DRAM cells
 +cannot be made smaller without jeopardizing their robustness. In this talk, I
 +identify two specific challenges to DRAM scaling, and present architectural
 +techniques to overcome them.
 +First, DRAM cells are becoming less reliable. By reading repeatedly from a cell,
 +I show that it is possible to corrupt the data in nearby cells. Such errors
 +arise from coupling effects between cells that have been placed too close to
 +each other. I demonstrate the errors on real systems, proving them to be a
 +security risk. After exploring the design space of potential remedies, I propose
 +a probabilistic mechanism that prevents the errors with low hardware overhead.
 +Second, DRAM cells are growing slower due to worsening process variation. To
 +tolerate the increasing latency, I propose to unlock more parallelism within a
 +DRAM chip. By making non-intrusive changes to DRAM architecture,​ I increase the
 +autonomy of each subarray, the smallest unit of DRAM floorplanning. This allows
 +different subarrays to be accessed in parallel, and reduces the effective
 +latency of main memory. ​
 +===== Bio =====
 +Yoongu Kim is a PhD candidate at Carnegie Mellon University working in computer
 +architecture with his advisor Onur Mutlu. Yoongu is worried about DRAM scaling,
 +but is also excited that the time is ripe for rethinking how we design and build
 +memory systems. He is a recipient of PhD Fellowships from Intel, Samsung, and
 +the Korea Foundation for Advanced Studies.