Heterogeneous Core Microarchitecture for Energy Efficiency

Tuesday April 23, 2013
HH D-210
4:30-6.00 pm

Chris Fallin (ECE, CMU)


A general-purpose core today is a compromise: it is designed to provide reasonable performance at reasonable energy efficiency for most code, but it is not necessarily the highest-performance or highest-energy-efficiency core design for all code. Nevertheless, single-thread performance and core energy efficiency remain fundamental problems in computer architecture today.

In order to provide better performance and efficiency, core architects over the past several decades have invented new microarchitectures – such as out-of-order engines, very-long-instruction-word (VLIW) engines, and many more specialized designs – each of which is suited to a particular type of code.

In this work, we propose a fine-grained heterogeneous core which combines many different types of execution backends. Our core design breaks the executing program into blocks of code, determines the best backend for each block, and then specializes the block for that backend. Our new core design obtains 40% average core power reduction at the same performance as a baseline aggressive out-of-order core while combining out-of-order, VLIW, and in-order backends. We conclude that fine-grained heterogeneity provides significant energy savings, and provides a substrate for further work on core-level heterogeneity.


Chris Fallin is a fourth-year Ph.D. student in Electrical & Computer Engineering at Carnegie Mellon University, where he is advised by Prof. Onur Mutlu. He works on high-performance, energy-efficient core microarchitecture and heterogeneous systems. He has also done work in the past on energy-efficient on-chip interconnects and on memory systems. Chris received his B.S. in Computer Engineering from Notre Dame in 2009 and his M.S. in ECE from Carnegie Mellon in 2011. He is supported by an NSF Graduate Research Fellowship, the Bertucci Fellowship, and a Qualcomm Innovation Fellowship Honorable Mention.

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