Table of Contents

Scale-Out Processors

Monday Oct. 8, 2012
CIC Panther Hollow Room

Boris Grot (EPFL)


A growing number of today’s most relevant applications are served online and run in large-scale datacenters characterized by thousands of servers and multi-megawatt power budgets. As Dennard scaling comes to a halt, experts are projecting exponential growth in datacenter power and performance requirements in the coming decade, driven by the rising popularity of the online service model. To efficiently meet the computing needs in the post-Dennard era, datacenters will rely on a new form of ISA – Integration, Specialization, and Approximation.
As a first step toward this post-Dennard ISA, we have developed Scale-Out Processors – a processor design methodology that maximizes performance per TCO on scale-out workloads running in large-scale datacenters. Using a metric of performance density, our methodology facilitates the design of optimal configurations, called pods, of cores, caches, and interconnect. Each pod is a stand-alone server-on-chip, a feature that avoids the expense and complexity of global (i.e., inter-pod) interconnect and coherence. As I will demonstrate, Scale-Out Processors yield higher performance, lower TCO, and better technology scalability over existing design alternatives.


Boris Grot is a post-doctoral researcher in the Parallel Systems Architecture Lab at EPFL. His research focuses on improving the efficiency of large-scale datacenters through advancements to server processor architectures, memory systems, and interconnects. Grot received his PhD in Computer Science from The University of Texas at Austin in 2011. His thesis addressed challenges of scalability and quality-of-service in on-chip networks of highly-integrated processor chips.

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