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seminars:seminar_12_08_09 [2017/09/20 22:02] (current)
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 +======StimulusCache:​ Boosting Performance of Chip Multiprocessors with Excess Cache ======
 +
 +Tuesday Dec. 08, 2009\\
 +Hamerschlag Hall D-210\\
 +4:00 pm\\
 +
 +{{:​me.small.jpg|}}
 +
 +**[[http://​www.cs.pitt.edu/​~abraham|Hyunjin Lee]]**\\
 +University of Pittsburgh\\
 +
 +=====Abstract=====
 +Technology advances continuously shrink on-chip devices. Consequently,​ the number of cores in a single chip multiprocessor (CMP) is expected to grow in coming years. Unfortunately,​ with smaller device size and greater integration,​ chip yield degrades sig-nificantly. Guaranteeing that all chip components function correctly leads to an unrealistically low yield. Chip vendors have adopted a design strategy to market partially functioning processor chips to combat this problem.
 +
 +The two major components in a multicore chip are compute cores and on-chip memory such as L2 cache. From the viewpoint of the chip yield, the compute cores have a much lower yield than the on-chip memory due to their logic complexity and well-established memory yield enhancing techniques. Therefore, future CMPs are expected to have more available on-chip memories than working cores.
 +
 +This paper introduces a novel on-chip memory utilization scheme called StimulusCache,​ which decouples the L2 caches of faulty compute cores and employs them to assist applications on other working cores. Our extensive experimental evaluation demonstrates that StimulusCache significantly im-proves the performance of both single-threaded and multithreaded workloads.
 +
 +
 +
 +=====Bio=====
 +Hyunjin Lee received a B.S. degree in Electrical Engineering from Seoul National University in 1999. He has been pursuing a Ph.D. degree in Computer Science from the University of Pitts-burgh since 2005. Prior to joining the University of Pittsburgh, he worked for the System LSI Di-vision of Samsung Electronics Co., Giheung, Korea, and contributed to the development of DVD players. His research interests are in the area of computer architecture,​ with particular fo-cus on performance,​ power, and reliability as-pects of memory hierarchy design for next-generation multicore processors
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