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seminars:seminar_12_02_08 [2017/09/20 22:02] (current)
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 +======T4: A highly-threaded server-on-a-chip with native support for heterogeneous computing======
  
 +Wednesday Feb. 8, 2012\\
 +CIC 4th floor Panther Hollow\\
 +4:00 pm\\
 +
 +{{:​seminars:​jared_smolens.jpg|}}
 +
 +**Jared Smolens (Oracle)**\\
 +
 +=====Abstract=====
 +This talk describes the microarchitecture of Oracle'​s newest processor, the UltraSPARC T4. T4 contains eight out-of-order processing cores that each dynamically support up to 8 threads to provide balanced single- and multi-threaded performance. T4 includes a shared 4 MB L3 cache, two on-chip memory controllers supporting buffered DDR3 memory, two 10 Gb Ethernet controllers,​ and two x8 PCI-Express 2.0 channels. The new SPARC processor cores incorporate dynamic resource allocation and thread-hog mitigation techniques across threads to maximize core throughput under homogenous and heterogeneous workloads.
 +\\
 +
 +=====Bio=====
 +Jared Smolens is a Principle Engineer at Oracle in Santa Clara, CA where he leads performance and power modeling of a future UltraSPARC processor core.  He started modeling of T4 at Sun Microsystems and followed the design through pre-silicon performance verification and post-silicon performance tuning. ​ He received his Ph.D. degree from Carnegie Mellon University in 2007 and has authored several papers on soft error detection.\\
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 +**[[seminars| Back to the seminar page]]**