This shows you the differences between two versions of the page.

Link to this comparison view

seminars:seminar_11_22_16 [2017/09/20 22:02] (current)
Line 1: Line 1:
 +====== LEAP Memory Compiler: Automatic Synthesis of Resource-Aware Memory Hierarchies ======
 +Tuesday November 22nd, 2016\\
 +Location: Panther Hollow Conference Room, CIC - 4th Floor\\
 +Time: 16:30PM\\
 +**[[http://​people.csail.mit.edu/​kfleming/​ | Kermin Fleming (Intel)]]**\\
 +As FPGAs have grown in size and capacity, FPGA memory systems have become
 +both richer and more diverse in order to support the increased computational
 +capacity of FPGA fabrics. ​ Gone are the days of a building BRAM caches
 +backed by a single DRAM: modern FPGA systems feature multiple off-chip
 +memory resources, often with asymmetric characteristics,​ and new fabric
 +resources like eSRAMs. Using complex FPGA memory resources, and using them
 +well, has become commensurately more difficult, especially in the context of
 +legacy designs ported from smaller, simpler FPGA systems. This growing
 +complexity necessitates the resource-aware compilers that can make good use
 +of memory resources on behalf of the programmer. In this work, we introduce
 +the LEAP memory compiler, which can synthesize application-optimized cache
 +networks for systems with multiple memory resources, enabling user programs
 +to automatically take advantage of the expanded memory capabilities of
 +modern FPGA systems. In our experiments,​ the optimized cache network
 +achieves up to 46% performance gain for throughput-oriented applications and
 +15% performance gain for latency-oriented applications,​ while increasing
 +design area by less than 5%.
 +This work is joint with Hsin-jung Yang and Michael Adler.
 +Kermin Fleming (BS, BS, MS, 2006)  obtained his Ph. D. in EECS from MIT in
 +2012, with a focus on network synthesis in FPGA systems. He now works are
 +Intel, where he researches reconfigurable architectures and software
 +**[[seminars| Back to the seminar page]]**