Table of Contents

Tuesday Nov. 10th 2015
Location: CIC Panther Hollow Room
Time: 4:30PM
Michael Adler
Principal Engineer, Technology Pathfinding and Innovation (TPI), Intel


LEAP Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies on FPGAs

FPGA programmers often find themselves bogged down in plumbing. In general purpose computation, high-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building increasingly complex systems. This separation has come only recently to FPGAs. It is still common for details of particular memory systems and devices to leak into user code, making it very difficult to port from one FPGA platform to another and even more difficult to take code optimized for one FPGA platform, switch to a new platform and take advantage of new resources.

LEAP, the Latency-Insensitive Environment for Application programming, is an open-source operating environment for FPGAs. Like an operating system on general purpose hardware, it provides abstract interfaces to classes of hardware such as memory and I/O devices. Beyond simple ease of programming and portability, this abstraction provides an opportunity to automate optimization of platform services for a particular application on particular hardware. In FPGAs, this platform-level malleability extends to the memory system. Since application kernels often use few memory resources, substantial memory capacity may be available to the platform for use on behalf of the user program.

The talk will cover the LEAP design philosophy and basic services and then discuss our current work on construction of application-specific memories, considering tradeoffs such as cache size, latency and timing.


Michael Adler is a Principal Engineer in the Technology Pathfinding and Innovation (TPI) group at Intel. After beginning his career on compiler back ends he has moved down the hierarchy toward processor simulation and microarchitecture research. His research is focused on the challenges of rapid specification of complex reconfigurable systems.

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