Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories

Tuesday March 1, 2011
Hamerschlag Hall D-210
4:00 pm

Santiago Bock
Computer Science Dept., University of Pittsburgh


Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties, they are prone to wear-out due to excessive write operations. Because wear-out is an important phenomenon, a number of endurance management schemes have been proposed. There is a trade-off between what techniques to use, depending on the range of bit cell lifetime within a device. This range in cell durability arises from effects due to process variation. In this paper, we describe modeling techniques to analyze trade-offs for endurance management based on the anticipated distribution of cell lifetime. This analysis considers two general endurance strategies (physical capacity degradation and physical sparing) under four distributions of cell lifetime (constant, linear, normal, and bimodal). The modeling techniques can be used to determine how much redundancy is needed when a sparing endurance strategy is adopted. With the correct choice of technique, the device lifetime can be doubled.


Santiago Bock is a third-year Ph.D. student in Computer Science at the University of Pittsburgh. He works under the supervision of Professors Bruce Childers, Rami Melhem and Daniel Mossé. His research interests include computer architecture, dynamic translation and runtime environments, virtual machines, compilers and operating systems. He is currently working on architectural techniques to improve the performance, power consumption and lifetime of phase change main memory. He received B.S. degrees in Computer Science and Computer Engineering from the University of the Andes in Bogota, Colombia.

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