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seminars:seminar_10_6_15 [2017/09/20 22:02] (current)
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 +====== Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM ======
 +Tuesday Oct. 6, 2015\\
 +Location: CIC Panther Hollow Room\\
 +Time: 4:30PM\\
 +[[http://​users.ece.cmu.edu/​~donghyu1/​|Donghyuk Lee (CMU)]]
 +Memory channel contention is a critical performance bottleneck in modern
 +systems that have highly parallelized processing units operating on large data
 +sets. The memory channel is contended not only by requests from different user
 +applications (CPU access) but also by system requests for peripheral data
 +(IO access), usually controlled by Direct Memory Access (DMA)
 +engines. Our goal, in this work, is to improve system performance by
 +eliminating memory channel contention between CPU accesses and IO accesses.
 +To this end, we propose a hardware-software cooperative data transfer
 +mechanism, Decoupled DMA (DDMA) that provides a specialized low-cost memory
 +channel for IO accesses. In our DDMA design, main memory has two independent
 +data channels, of which one is connected to the processor (CPU channel) and the
 +other to the IO devices (IO channel), enabling CPU and IO accesses to be
 +served on different channels. System software or the compiler identifies which
 +requests should be handled on the IO channel and communicates this to the DDMA
 +engine, which then initiates the transfers on the IO channel. ​ By doing so, our
 +proposal increases the effective memory channel bandwidth, thereby either
 +accelerating data transfers between system components, or providing
 +opportunities to employ IO performance enhancement techniques (e.g., aggressive
 +IO prefetching) without interfering with CPU accesses.
 +We demonstrate the effectiveness of our DDMA framework in two scenarios:
 +(i) CPU-GPU communication and (ii) in-memory communication (bulk data
 +copy/​initialization within the main memory). By effectively decoupling accesses
 +for CPU-GPU communication and in-memory communication from CPU accesses, our
 +DDMA-based design achieves significant performance improvement across a wide
 +variety of system configurations.
 +I am a Ph.D. student at Carnegie Mellon, working with my advisor Prof. Onur
 +Mutlu in the SAFARI research group, part of the Computer Architecture lab at
 +Carnegie Mellon (CALCM). My research interests are in efficient memory
 +subsystem, DRAM architecture,​ and bioinformatics.
 +**[[seminars| Back to the seminar page]]**