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seminars:seminar_10_26_10 [2017/09/20 22:02] (current)
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 +====== Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? ======
 +Tuesday Oct. 26, 2010\\
 +Location: Hamerschlag Hall D-210\\
 +Time: 4:00PM\\
 +**Eric Chung**\\
 +Carnegie Mellon University\\
 +To extend the exponential performance scaling of future chip multiprocessors,​ improving energy efficiency has become a first-class priority. ​ Single-chip heterogeneous computing has the potential to achieve greater energy efficiency by combining traditional processors with unconventional cores (U-cores) such as custom logic, FPGAs, or GPGPUs. ​ Although U-cores are effective at increasing performance,​ their benefits can also diminish given the scarcity of projected bandwidth in the future. To understand the relative merits between different approaches in the face of technology constraints,​ this work builds on prior modeling of heterogeneous multicores to support U-cores. ​ Unlike prior models that trade performance,​ power, and area using well-known relationships between simple and complex processors, our model must consider the less-obvious relationships between conventional processors and a diverse set of U-cores. ​ Further, our model supports speculation of future designs from scaling trends predicted by the ITRS road map. The predictive power of our model depends upon U-core-specific parameters derived by measuring performance and power of tuned applications on today'​s state-of-the-art multicores, GPUs, FPGAs, and ASICs. ​ Our results reinforce some current-day understandings of the potential and limitations of U-cores and also provides new insights on their relative merits.
 +Eric Chung is a PhD candidate advised by Prof. James C. Hoe at the Com-puter Architecture Lab at Carnegie Mellon. ​ He is in interested in the inter-section of computer architecture and reconfigurable computing.
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