A Process Variation Perspective on 3-D Integrated Multi-processor Architectures

Tuesday Feb. 9, 2010
Hamerschlag Hall D-210
4:00 pm


Siddharth Garg
Carnegie-Mellon University


3D integration technology is a promising solution for the increasing on-chip communication costs, both in terms of latency and power dissipation, in scaled CMOS technologies. While the thermal concerns associated with 3D integration have been extensively addressed, relatively little research has addressed the impact of process variations – another growing problem with technology scaling – on the performance of systems that make use of 3D integration.

In this talk, we will present 3D-GCP, a high-level model for the impact of process variations on 3D IC performance. Using this model we will show that, in fact, 3D ICs suffer from more severe performance degradation under the impact of process variations compared to equivalent 2D implementations. Furthermore, the performance hit is more severe as the number of layers in the 3D stack is increased, potentially eliminating the performance advantages of 3D integration.

Motivated by these predictions, we will present a process-variation aware 3D assembly strategy that attempts to mitigate the loss in performance by speed-binning the tiers of the 3D stack prior to 3D assembly and using this information to maximize the number of assembled systems that meet a specified performance target. Experimental results on both application-specific and general purpose multi-core platforms demonstrate that significant yield improvements are achieved using the proposed techniques.


Siddharth Garg is currently a post-doctoral fellow in the Electrical and Computer Engineering Department at Carnegie-Mellon University. He received in a Ph.D. in Electrical and Computer Engineering also from CMU, a Masters degree in Electrical Engineering from Stanford University and a Bachelors degree in Electrical Engineering from the Indian Institute of Technology (IIT) Madras. His research interests include design methodologies and tools for process-variation and energy aware multi-processor architectures and 3D integration technology. He has won best paper awards at the ISQED 2009 and the SRC Techcon 2009, and a best paper nomination at DATE 2009.

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