ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers

Tuesday Sep. 15, 2009
Hamerschlag Hall D-210
4:00 pm

Yoongu Kim
Carnegie Mellon University


The large disparity between CPU and memory speed, known as the “memory wall”, is one of the most severe performance bottlenecks in computer systems. In modern multicore archi-tectures, this problem is further exacerbated as cores must compete among themselves for access to memory. Therefore, a scheduling algo-rithm is employed by the memory controller to resolve this contention in a way that reduces memory access latency and improves overall system throughput. Unfortunately, previous scheduling algorithms require very fine-grained intervention that increases hardware complexity and, consequently, limits their scalability to mul-tiple memory controllers. In this talk, I will introduce a memory scheduling algorithm that increases system throughput by utilizing high-level memory access behavior of threads, and yet is simple enough to remain scalable. Motivated by the discovery that memory access behavior follows a Pareto distri-bution, ATLAS (Adaptive per-Thread Least-Attained-Service) is able to make future scheduling decisions based on threads’ past memory accesses. Evaluated across a wide variety of workloads and system configurations, ATLAS is shown to consistently improve system throughput compared to previously proposed memory scheduling algorithms.


Yoongu Kim is a second year Ph.D. student in the Electrical and Computer Engineering department. He completed his Bache-lor’s Degree in Electrical Engineering at Seoul National Univer-sity in 2005. He researches better ways to resolve contention for shared system resources in multicore architectures. He is being advised by Onur Mutlu and Mor Harchol-Balter.

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