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seminars:seminar_04_03_14 [2017/09/20 22:02] (current)
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 +======Title:​ Memory Architectures for Emerging Technologies and Workloads======
 +==== Rajeev Balasubramonian ====
 +== Thursday, April 3rd, 4:​00pm-5:​00pm ==
 +== Panther Hollow, CIC 4th floor ==
 +The memory system will be a growing bottleneck for many workloads
 +running on high-end servers. ​ Performance improvements from
 +technology scaling are also expected to decline in the coming decade.
 +Therefore, new capabilities will be required in memory devices and
 +memory controllers to achieve the next big leaps in performance and
 +energy efficiency. ​ Some of these capabilities will be inspired by
 +emerging workloads (e.g., in-memory big-data, approximate computing,
 +co-scheduled VMs), some will be inspired by new memory technologies
 +(e.g., 3D stacking). ​ The talk will discuss multiple early-stage
 +projects in the Utah Arch lab that focus on DRAM parameter variation,
 +near-data processing, and memory security.
 +Rajeev Balasubramonian is an Associate Professor at the School of
 +Computing, University of Utah.  He received his B.Tech in Computer
 +Science and Engineering from the Indian Institute of Technology,
 +Bombay in 1998. He received his MS (2000) and Ph.D. (2003) degrees
 +from the University of Rochester. ​ His primary research areas
 +include memory hierarchies and interconnects. ​ Prof. Balasubramonian
 +is a recipient of an NSF CAREER award, an IBM Faculty Partnership
 +award, an HP IRP award, and various teaching awards at the University
 +of Utah.  He has co-authored papers that have been selected as
 +IEEE Micro Top Picks (2007 and 2010) and that have received best
 +paper awards (HiPC'​09 and PACT'​10).