FPGA-based Computing in the Era of AI and Big Data

Wednesday March 28, 2019
Location: CIC Panther Hollow
Time: 9:00AM-10:00AM


The continued rapid growth of data, along with advances in Artificial Intelligence (AI) to extract knowledge from such data, is reshaping the computing ecosystem landscape. With AI becoming an essential part of almost every end- user application, our current computing platforms are facing several challenges. The data-intensive nature of current AI models requires minimizing data movement. Furthermore, interactive intelligent datacenter-scale services require scalable and real-time solutions to provide a compelling user experience. Finally, algorithmic innovations in AI demand a flexible and programmable computing platform that can keep up with this rapidly changing field. We believe that these trends and their accompanying challenges present tremendous opportunities for FPGAs. FPGAs are a natural substrate to provide a programmable, near-data, real-time, and scalable platform for AI analytics. FPGAs are already in several places where data flows throughout the computing ecosystem (e.g., smart network/storage, near image/audio sensors, accelerator cards). Intel FPGAs are System-in-Package (SiP), scalable with 2.5D chiplets. They are also scalable at datacenter- scale as reconfigurable cloud, enabling real-time AI services. Using overlays, FPGAs can be programmed through software without needing long-running RTL synthesis. With further innovations, and leveraging their existing strengths, FPGAs can leap forward to realize their true potentials in AI analytics.

In this talk, we first discuss the current trends in AI and big data. We then present trends in FPGA and opportunities for FPGAs in the era of AI and big data. Finally, we highlight our research efforts on software-programmable overlay for AI inference on current Intel FPGAs, experimental FPGA SiP with 2.5D AI chiplets, and scaling to multiple FPGAs in an Intel Xeon server.


Dr. Eriko Nurvitadhi is a senior research scientist and manager of the FPGA Research Lab at Intel Labs. He works on hardware accelerator architectures (e.g., FPGAs, ASICs) for AI and data analytics, with over 30 academic publications and 20 patent filed/issued in this area. His research has contributed to Intel’s FPGA and ASIC solutions for AI. He co-founded Intel academic programs on FPGAs (HARP, ISRA). He received his PhD in Electrical and Computer Engineering from Carnegie Mellon University.