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seminar_10_11_17 [2017/10/06 11:46] (current)
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 +====== Using Vivado-HLS for Structural Design: a NoC Case Study ======
 +Wednesday October 11, 2017\\
 +Location: CIC Panther Hollow Room\\
 +Time: 4:30PM\\
 +High-level synthesis(HLS) is a promising approach to ease FPGA development efforts by raising programming abstraction from register-transfer level(RTL) to high level languages. Vivado-HLS, a widely used HLS tool that maps C function to hardware module, has demonstrated its success in many algorithmic designs. ​
 +In this talk, I'll introduce a design study that assesses the effectiveness of applying Vivado-HLS in structural design, where we want precise bit- and cycle-level control. We succeeded in using Vivado-HLS to produce router and NoC modules that are exact cycle- and bit-accurate replacements of our RTL-based reference. Furthermore,​ the routers and NoCs resulting from HLS and RTL are comparable in resource utilization and critical path delay. Our experience subjectively suggests that HLS is able to simplify the design effort even though much of the structural details had to be provided in the HLS description through a combination of coding discipline and explicit pragmas. ​
 +Zhipeng Zhao is a fourth year Ph.D. student in the Department of Electrical and Computer Engineering at CMU advised by Prof. James Hoe. His research focuses on High-level Synthesis, Network-on-Chip,​ and distributed FPGA acceleration system. ​