Wednesday April 5, 2017
Location: CIC Panther Hollow Room
Guanglin Xu (CMU)
High-level Synthesis (HLS) improves the productivity of FPGA designers by using compilers to generate RTL code previously hand-written. However, a practical limitation arises when a hardware design cannot be efficiently synthesized from the HLS compiler. In this talk, we discuss the limitations of loop concurrency and interface synthesis in a production HLS compiler in generating efficient Pease FFT kernels. We then show the advantage of coding with an event-based dataflow paradigm. Using this approach, we obtain kernels comparable to hand-written RTL implementations. Our results suggest that event-based dataflow paradigm is potentially a powerful solution for obtaining high quality designs from HLS.
Guanglin Xu is a 3rd year PhD student co-advised by Prof. James Hoe and Prof. Franz Franchetti. His research is focused on FPGA, High-level synthesis and automatic code generation.