Tuesday Dec. 8, 2015
Location: CIC Panther Hollow Room
The crossbar is a popular network topology for on-chip networks that offers uniform latency and low complexity. However, as the number of network nodes increases, crossbars typically scale poorly in area, power, and latency/throughput. To better understand the design space, we have developed an on-chip crossbar modeling tool based on analytical models calibrated using circuit-level simulation results in 40nm CMOS. We present a design space exploration showing how crossbar area, power, and performance vary across input/output node number, data width, wire parameters, and circuit implementation. Using the modeling results, we identify a design point that demonstrates ~2x higher throughput, ~1.4x lower power and ~1.2x lower area compared to previous published designs. Further, to improve the crossbar scaling, we propose building modular crossbar switches that can perform better at high radices than the monolithic designs. The sub-blocks are designed to achieve high throughput by limiting the design area and parasitic wire parameters. They are arranged in a flow-through, pipelined scheme to maintain linear performance scaling and achieve constant throughput with radix scaling. Further, small sub-block sizing and modularity enable using power supply reduction and power gating to improve energy efficiency.
Cagla is a PhD student in the Department of Electrical and Computer Engineering at Carnegie Mellon University, and she has been collaborating with Oracle Labs for the last five years. Her research interests include energy efficient, high-speed circuit design and interconnection networks. She received her B.S. in Electrical and Electronics Engineering from Sabanci University, Turkey in 2009.