Tuesday Jan. 26, 2010
Hamerschlag Hall 1112 (Note the change in location)
1:00 pm (Note the special time)
We present an end-to-end simulation framework that is capable of simulating High-Performance Computing (HPC) systems with hundreds of thousands of interconnected processors. It provides semantically correct replay of MPI application traces and maintains reasonable simulation details of both the processors in general and specifically the interÂconnection network. Among other things, it features several network topologies, flexible routing schemes, arbitrary application task placement, point-to-point statistics collection, and data visualization. This tool has been used for high-level system design as well as for performance projection and application tuning of future HPC systems.
As a case study, we use the tool to evaluate two complementary techniques to manage the power consumption of large-scale systems with a packet-switched interconnection network. First, we propose Thrifty Interconnection Network (TIN), where the network links are activated and de-activated dynamically with little or no overhead by using inherent system events to trigger link activation or de-activation timely. Second, we propose Wavefront Power Shifting (WPS) that dynamically shifts the power budget between the compute nodes and the interconnection network. WPS and TIN together activate and train the links in the interconnection network, just-in-time before the network communication is about to happen, and put them into a low-power mode thriftily when communication is finished, hence reducing unnecessary network power consumption. At the mean time, the compute nodes can absorb the extra power budget shifted from the thrifty network and increase their operating frequency for higher computing speed. Our simulation results on a set of real world HPC workload traces show that TIN and WPS together achieve on average 35% network power reduction, 5% system performance improvement, and 7% system energy reduction. Some other work will be discussed as well.
Jian Li is a research staff member with the Novel Systems Architecture group at IBM Austin Research Laboratory. He holds a Ph.D. degree in Electrical and Computer Engineering from Cornell University. He has worked in the areas of architectural support for power- and variation-aware computing, interconnection network design for high-performance computing systems, workload-driven three-dimensional (3D) integration architecture, architectural applications of nonvolatile memory (NVM) and storage class memory (SCM), energy-efficient interconnection networks, and cache/memory subsystem design, with a strong emphasis on entertaining his family members in Austin, Texas.