Undergrad Research Project - Lunar Rover SBC Revision C FPGA Video Processing

Spring 2017

Bradley Powell
Red Whittaker
Project description

During the previous semester (Fall 2016), the single board computer for the Lunar Rover was updated to revision C, featuring new sensors, motor control, new communication lines, and a new FPGA (Cyclone V 5CEBA4F17I7N). Since the brassboards were only assembled at the end of last semester, bare metal testing for the important pieces of the new FPGA design (the CSI-II receiver and the new JPEG compressor) has not been started. Furthermore, the updates to the communication protocols between the chips on the board mean that the embedded code on the NIOS II will need to be updated and tested. Finally, the new FPGA is an intermediate choice and is untenable for flight, due to lack of radiation shielding and unstable physical connection to the board.

Therefore the focus for the research in Spring 2017 will be a combination of bare metal testing and debugging for the new FPGA designs, updating the NIOS-II software to be compatible with the new board revision, and most importantly, acquiring or at least locating a space-capable FPGA to put on the flight revision. The last part will include talking with manufacturers about possible choices for the FPGA, which may involve either a series switch or an entire manufacturer switch. Both choices will require refactoring the FPGA design to fit the new architecture, with the manufacturer switch being the more drastic of the two.

As always, supporting continuing work on the Hercules software by the avionics team will take priority if changes need to be made. The overarching goal of this project will be to focus the design to be flight ready by the launch date.

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