Undergrad Research Project - Scheduling Image Processing Pipelines on FPGAs

Spring 2017

Teguh Hofstee
Kayvon Fatahalian
Project description

Objective: The objective of this project is to extend the image processing pipeline scheduling created by Mullapudi et al. for Halide to FPGAs. Current systems such as Rigel are restricted to largely being hand scheduled, as prior work had difficulty enumerating and exploring the design space.

Method: As place and route is still vendor specific, we want to create something that can explore the design space of a low level image processing IR and quickly explore the design space, estimating performance/area tradeoffs so a subset of designs could be fully explored through the time intensive place and route. In collaboration with the Rigel group at Stanford, we aim to improve their existing IR and create an autoscheduler for the higher level loops of image processing pipelines, which would be aided by a lower level DAG optimizer.

Anticipated Results: Automatic scheduling of line-buffer pattern pipelines should be fairly straightforward, and after that we will try to extend the autoscheduler to more varied pipelines.

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