Undergrad Research Project - Lunar Rover Avionics and Video Handling

Fall 2016

Bradley Powell
Red Whittaker
Project description

Revision B of the current Lunar Rover electronics board is controlled primarily by a Cyclone IV E-series FPGA. Over the summer of 2016, much of the onboard avionics and video streaming/recording was completed. However, much work remains to be done to get the Rover's electronics board ready for further board upgrades and eventually flight.

The JPEG compressor designed over the summer must be redesigned for space optimization, as it currently takes up over twice the space available on the current FPGA, and despite the likely acquisition of new hardware, this is still unreasonable. The JPEG compressor itself must be tested on chip once a large enough one is available, since software verification can be unreliable. Furthermore, the current DVP protocol must be ported over to CSI-2, a significantly more complex protocol necessitated by the need to move the camera to a different location on the board. Once these are completed, depending on the status of the other teams, work can be started on the motor control.

While the main focus of this research will be the FPGA HDL design, much work will be put towards supporting and contributing to the embedded software on the Nios II, the CPLD HDL design, and any IC work that needs to be done either for improving the current board or designing Revision C.

Return to project list