Undergrad Research Project - Channelized Memory Interface for the Intel HARP FPGA Acceleration Platform

Spring 2016

Neil Ryan
James Hoe
Project description

The Intel Heterogeneous Architecture Research Platform (HARP) project looks to use Intel technology to develop the state of accelerator-based computing platforms. This project will build on existing HARP infrastructure by added a more advanced memory management interface for the FPGA. We will work to use the larger cache of the CPU to improve memory access times for the FPGA's computation. We will begin by adding static support for modules with access patterns non-spatial relative to other modules to forward memory requests to the CPU. If all bodes well, we will expand support for dynamic support, where memory accesses are determined to be spatial or non-spatial in-flight and are conditionally routed to the CPU's memory subsystem. We expect reasonable performance improvements to the HARP platform as a result of this project. If the above is completed, additional work will be done to further the performance of the HARP FPGA acceleration platform.

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