Undergrad Research Project - RTL Implementation of AlexNet CNN

Spring 2016

Sohil Shah
Raj Rajkumar
Project description

This project’s objective is to design and implement a software simulation model of a real-time, hardware, object-classification system from input images. The simulator will also help determine the feasibility of a field-programmable gate array (FPGA) implementation of the system. First, we will build software to receive test images from a camera or a file. Second, we will use register-transfer level (RTL) code to implement a hardware simulation of an AlexNet convolutional neural network (CNN) that classifies objects in an image. Third, these two parts will be integrated using the tool Verilator, allowing the system to receive an image and classify objects in that image. Finally, we will use a synthesis tool, such as Synopsys Design Compiler, to analyze the logic area cost of our design. Ultimately, the simulator will be able to receive images and classify objects in real-time. The synthesis tool analysis of the RTL will determine whether an FPGA implementation is feasible. If it is feasible, the RTL description of the CNN will be in a state that can be easily synthesized and programmed onto an FPGA.

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