Undergrad Research Project - Memory Hierarchy Architecture

Fall 2011

Chan Sik Kim
James Hoe
Project description

This project is intended to find out a better way to optimize memory architecture (cache and TLB). Throughout last summer, I built a trace-driven simulator, which simulates L1Icache, L1Dcache, L2_unified, and TLB under LRU replacement policy. Throughout this semester, I will first review most recent research papers about memory architecture and test them with my simulator. Then I will propose and evaluate my own enhancements in memory architecture.

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